1. Technical Field
The present application relates to heat-treating of workpieces such as semiconductor wafers, and more particularly, to methods, apparatus and computer-readable media for determining a shape of an irradiance pulse to which a workpiece such as a semiconductor wafer is to be exposed during a thermal cycle.
2. Description of Related Art
Numerous applications involve heat-treating a workpiece. For example, in the manufacture of semiconductor chips such as microprocessors and other computer chips, a semiconductor wafer such as a silicon wafer is subjected to an ion implantation process, which introduces impurity atoms or dopants into a surface region of a device side of the wafer. The ion implantation process damages the crystal lattice structure of the surface region of the wafer, and leaves the implanted dopant atoms in interstitial sites where they are electrically inactive. In order to move the dopant atoms into substitutional sites in the lattice to render them electrically active, and to repair the damage to the crystal lattice structure that occurs during ion implantation, it is necessary to anneal the surface region of the device side of the wafer by heating it to a high annealing temperature.
However, the high temperatures required to anneal the device side also tend to produce undesirable effects using existing technologies. For example, diffusion of the dopant atoms deeper into the silicon wafer tends to occur at much higher rates at high temperatures, with most of the diffusion occurring within close proximity to the high annealing temperature required to activate the dopants. Decades ago, diffusion was not as significant a barrier, and the relatively large and deep device sizes prevailing at those times could be manufactured by simply heating the entire wafer isothermally to an annealing temperature and then holding it at the annealing temperature for a relatively long time, such as minutes or even hours, for example.
However, in view of steadily increasing demand for greater performance and smaller device sizes, it is now necessary to produce increasingly shallow and abrupt junctions with controlled diffusion depths. As a result, diffusion depths which would have been considered negligible in the recent past are no longer tolerable today, and likewise, diffusion depths which are tolerable today will become unacceptable in the near future.
In light of the above difficulties, commonly owned U.S. Pat. Nos. 6,594,446, 6,941,063, 6,963,692, 7,445,382, 7,501,607 and 7,616,872 (which are hereby incorporated herein by reference) disclose various methods of annealing a semiconductor wafer, such as a flash-assisted rapid thermal processing (fRTP™) cycle, for example. An example of an fRTP™ cycle may involve pre-heating the entire wafer to an intermediate temperature at a ramp rate slower than the thermal conduction rate through the wafer, then heating the device side of the wafer at a rate much faster than the thermal conduction rate, which may be achieved by exposing the device side to an irradiance flash. As an illustrative example, the wafer may be pre-heated to an intermediate temperature such as 600° C. for example, by irradiating the substrate side with an arc lamp to heat the entire wafer at a rate such as 150° C. per second, for example. The device side may then be exposed to a high-intensity flash from a flash lamp, such as a one-millisecond flash, to heat only the device side to an annealing temperature such as 1300° C., for example. Due to the rapid heating rate of the device side during the flash (in excess of 105° C./s), the bulk of the wafer remains at the intermediate temperature, and acts as a heat sink to rapidly cool the device side following the flash. Due to the rapidity of the flash-heating stage and the subsequent cooling stage, the device side of the wafer spends far less time at or near the annealing temperature in comparison to traditional isothermal heating cycles in which the entire wafer is heated to the annealing temperature. As a result, dopant activation and crystal lattice repair are achieved with far less undesirable dopant diffusion than traditional isothermal heating cycles.
Such flash-assisted annealing methods, which involve rapidly heating the device side of the wafer to a substantially higher temperature than the bulk of the wafer, tend to cause the device side to thermally expand at a greater rate than the rest of the wafer. This rapid expansion of the device side relative to the bulk of the wafer may cause the wafer to deform rapidly and significantly.
Due to the extreme rapidity at which the device side of the wafer is heated (in the course of a 1-millisecond flash, for example, much faster than a typical thermal conduction time in the wafer), the deformation of the wafer may occur sufficiently rapidly that the edges of the wafer tend to move rapidly downward. If the wafer is supported by conventional support pins near its edges, the thermal deformation of the wafer may apply large downward forces to the support pins, potentially damaging or destroying both the pins and the wafer. Such forces may also cause the wafer to launch itself vertically upward from the support pins, which may result in further damage to the wafer as the wafer falls back down and strikes the pins. If the wafer is supported by support pins located further radially inward, the edges of the wafer may rapidly deform downward and strike a support plate above which the wafer is supported, potentially damaging or destroying the wafer. In addition, due to the rapidity at which such thermal deformation occurs, the initial velocities imparted to the various regions of the wafer tend to cause the wafer to overshoot the equilibrium minimum stress shape and rapidly oscillate or vibrate, resulting in additional stress and potentially damaging or destroying the wafer.
Commonly owned U.S. Pat. No. 7,501,607 discloses use of gas pressure between the wafer and a support plate above which it is supported, to dampen such motion and vibration of the wafer. Other approaches to suppressing or accommodating such motion and vibration are disclosed in commonly owned pending U.S. Patent Application Publication Nos. US 2004/0178553 and US 2008/0157452 (which are hereby incorporated herein by reference), for example.